Design & Reuse
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70 IP
51
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
52
0.0
LDPC Decoder IS-GPS-800D IP
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
53
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
54
0.0
5G-NR LDPC Encoder
The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high th...
55
0.0
WiMAX IEEE802.16e Transceiver IP Core
The transceiver is designed to be used together with an RF tuner and ADC/ DAC converters. The system has internal state machine to control the operat...
56
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Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....
57
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Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...
58
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Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one it...
59
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Nonbinary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
60
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Doppler Channel IP Core
The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...
61
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ISDB-S3-LDPC-BCH Decoder IP
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...
62
0.0
LTE Turbo Decoder
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the interna...
63
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DVB-C Demodulator IP Core
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine ...
64
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DVB-C2 LDPC Decoder IP
The Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
65
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DVB-C2 LDPC/ BCH Decoder IP Core
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes co...
66
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DVB-S2-LDPC-BCH IP
The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broad...
67
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DVB-S2X Modulator IP Core
IP core has two ways of forming the output spectrum: -Baseband (using odati and odatq), ifreq equal 0 -Intermediate frequency (using odati), ifreq not...
68
0.0
DVB-S2X-LDPC Decoder IP
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...
69
0.0
DVB-T2-LDPC-BCH IP
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC (Forward Error Correction) sub-system is needed. FEC...
70
0.0
DVB-T2/Lite LDPC Decoder IP
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...